1. Field of the Invention
The present invention relates to a high breakdown voltage output circuit for shifting a level of a low-voltage output signal to output a high-voltage output signal.
2. Description of the Related Art
In general, since an IC for driving a light-emitting display such as an electroluminescence display or a plasma display panel requires a high drive voltage, drive ICs having high breakdown voltage characteristics have been used. In an output circuit in the drive IC, high breakdown voltage characteristics, a short switching time, and low power consumption have been demanded. For this reason, a CMOS circuit is used to receive an input signal to output a low-voltage signal, and a high-voltage signal obtained by shifting the level of the low-voltage signal is output from a push-pull output stage.
FIG. 1 is a circuit diagram showing a conventional output circuit used for the above-mentioned drive IC. A CMOS inverter 23 is inserted between a low-voltage power supply V.sub.DD and a ground voltage V.sub.SS. In the CMOS inverter 23, the gates and drains of a p-channel MOS transistor 21 and an n-channel MOS transistor 22 are commonly connected to each other. The emitter of a high breakdown voltage pnp transistor 24 is connected to a high-voltage power source V.sub.CC. The transistor 24 has a multicollector structure. A first collector 25 is connected to the base of the transistor 24. The base of the pnp transistor 24 is connected to the drain of an n-channel DMOS (double diffused MOS) transistor 26, the gate of which is connected to a common drain of the CMOS inverter 23, and the source of which is connected to the ground voltage V.sub.SS. A second collector 27 of the pnp transistor 24 is connected to the drain of an output pull-down n-channel DMOS transistor 28, the gate of which is connected to a common gate of the CMOS inverter 23, and the source of which is connected to the ground voltage V.sub.SS. In addition, the gate of an output pull-up n-channel DMOS transistor 29 is connected to the second collector 27. The drain of the transistor 29 is connected to the high-voltage power source V.sub.CC, and a cathode-anode path of a Zener diode 30 is connected to a source-drain path of the transistor 29. An input signal IN is supplied from the common gate of the CMOS inverter 23, and an output signal OUT is output from the source of the n-channel DMOS transistor 29 through an output terminal.
In the circuit with the above arrangement, when the input signal IN is set at "L" level, the transistor 21 in the CMOS inverter 23 is turned on, and the transistor 22 is turned off. Therefore, the n-channel DMOS transistor 26 is turned on in response to the output signal set at V.sub.DD level. Therefore, the pnp transistor 24 having the multicollector structure is turned on, and a voltage drop occurs across the Zener diode 30 in response to this ON current, thus turning on the n-channel DMOS transistor 29. As a result, a parasitic capacitance of the output terminal is charged, and the output OUT goes to "H", i.e., V.sub.CC level.
When the input signal IN is set at "H" level, the transistor 21 in the CMOS inverter 23 is turned off, and the transistor 22 is turned on. Therefore, the transistor 26 is turned off. The transistor 28 is turned on in response to the input signal IN set at "H" level. As a result, the transistor 29 is turned off, and the output Out goes to "L" level.
The high-voltage power supply V.sub.CC is used in the circuit shown in FIG. 1. Therefore, even if a slight current flows, power consumption is high. In order to minimize the power consumption, an operation current of the level shift transistor 24 must be decreased. Conventionally, an ON current of the transistor 26 has been decreased to solve the above problem. However, the MOS transistor 26 and the transistor 24 constitute a current mirror circuit. Therefore, when the ON current of the MOS transistor 26 is decreased, a current supplied to the collector of the transistor 24 is also decreased. During a pull-up operation of the output, a predetermined voltage drop occurs across the Zener diode 30 in response to a current supplied to the collector 27 of the transistor 24. The gate potential of the MOS transistor 29 is increased, and the transistor 29 is turned on. At this time, the gate potential of the MOS transistor 29 is increased while the parasitic capacitance in the drain of the MOS transistor 28 is charged. At this time, a delay time .DELTA.t of a change in gate potential of the MOS transistor 29 with respect to the gate potential of the MOS transistor 26 is as follows: EQU .DELTA.t=C/i (1)
where C is a parasitic capacitance of a node of the gate of the MOS transistor 29 including the parasitic capacitance in the transistor 28, and i is a current supplied to the collector 27 of the transistor 24. Therefore, when a collector current of the transistor 24 is decreased, the delay time .DELTA.t is increased. The element sizes of the MOS transistors 28 and 29 are set to be large to realize a sufficiently high load drive capability in order to pull-up or -down the output. Therefore, the value of the parasitic capacitance C is also large. For this reason, a long signal propagation time is present between the input and output operations, and a high-speed operation cannot be achieved in the conventional circuit.